Microsoft Unveils Maia 300: Its Third-Gen In-House AI Inference Chip

Microsoft Unveils Maia 300: Its Third-Gen In-House AI Inference Chip

Other · PC Hardware News

Microsoft has announced the Maia 300, its third-generation in-house AI chip, designed to become the primary AI inference system for Microsoft's cloud products starting in 2027. The company claims it delivers 40% more tokens per megawatt than leading GPU-based systems and up to 7x the rack-scale token throughput of its predecessor, Maia 200.

Microsoft has announced the Maia 300, its third-generation custom AI chip, positioned to become the "primary AI inference system" for Microsoft's own products and services. According to Scott Guthrie, executive vice president of Microsoft's cloud group, the company expects Maia 300 to deliver 40 percent more tokens per megawatt compared to leading GPU-based systems, with a full 96-accelerator rack configuration offering up to 7x the rack-scale token throughput of the previous-generation Maia 200.

The chip uses a new chiplet architecture built on TSMC's N2P process node, separating compute, memory controller, and I/O functions onto different pieces of silicon. Microsoft's Azure hardware and infrastructure team says this increases the silicon area dedicated to compute performance and lets each function use whichever technology best suits its role. Per HotHardware, the Maia 300 pairs 8 stacks of HBM4 memory for 18.0 TB/s of peak bandwidth with a 950-watt TDP, and also uses on-die SRAM as a software-managed scratchpad to reduce how often the chip needs to reach out to HBM.

Maia 300 follows the Maia 200, which only launched in January and is already running production workloads including Microsoft Copilot, GitHub Copilot, Microsoft Foundry, and Microsoft's own AI models across the US, Europe, and Australia. Guthrie calls Maia 200 "the best performing AI infrastructure in our fleet," and describes Maia 300 as a complete system built for newer workload types: long-context reasoning, latency-sensitive conversational experiences, and sustained multi-step agentic tasks. Microsoft says it plans to scale the Maia family to multi-gigawatt deployments starting in 2027, reducing its reliance on Nvidia and AMD GPUs for internal AI infrastructure.

Mustafa Suleyman, Microsoft's AI CEO, framed the chip as central to Microsoft's broader AI ambitions, saying the company needs to "work across the full stack, all the way down to the silicon" and co-design a platform it owns alongside its models. The Maia 300 also supports advanced low-precision datatypes, including enhanced MXFP4, to shrink memory footprints and bandwidth use, and relies on tensor-parallel interconnects using a custom transport protocol over standard Ethernet to scale from single racks up to large multi-rack datacenter deployments.

What We Know

Spec Detail
Successor To Maia 200
Process Node TSMC N2P (compute chiplets)
Architecture Modular chiplet design separating compute, memory controller, and I/O
Memory 8 stacks of HBM4, 18.0 TB/s peak memory bandwidth
TDP 950 watts
Rack Configuration 96 accelerators, 167-kilowatt power envelope, 27.6 TB aggregate HBM, 1.7 PB/s aggregate HBM bandwidth
Claimed Efficiency Gain 40% more tokens per megawatt vs. leading GPU-based systems
Production Rollout Starting in 2027
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Frequently Asked Questions

What is the Microsoft Maia 300?

It's Microsoft's third-generation in-house AI chip, designed as an inference-first architecture for cloud AI workloads including long-context reasoning and agentic tasks.

When will Maia 300 be available?

Microsoft says Maia 300 will start rolling out to production in 2027, with multi-gigawatt deployments scaling from that point.

How does Maia 300 compare to Maia 200?

Microsoft claims Maia 300 delivers up to 7x the rack-scale token throughput of Maia 200 in a full 96-accelerator configuration, along with 40% more tokens per megawatt than leading GPU-based systems.

What are the Maia 300's key specs?

It features 8 stacks of HBM4 memory delivering 18.0 TB/s of peak bandwidth, a 950-watt TDP, compute chiplets built on TSMC's N2P process, and a modular architecture separating compute, memory controller, and I/O functions.

Sources: The Verge · HotHardware